The exemplary embodiments of the present invention relate to a non-volatile memory device, and more particularly, to a technology for improving a fast verify operation of a non-volatile memory device.
Memory devices are divided into a volatile memory device and a non-volatile memory device according to whether data are maintained or not when a power supply is cut off. The volatile memory device is a memory device whose data are not stored when a power supply is cut off, and examples of the volatile memory include a dynamic random access memory (DRAM) and static random access memory (SRAM). The non-volatile memory device is a memory device whose data are stored even when a power supply is cut off, and examples of the non-volatile memory include a flash memory.
Main operations of the non-volatile memory device include an erase operation, a read operation, a programming operation. Herein, what determines the characteristics of a product is write performance related to the programming operation. Write performance is a value defined as the amount of data that may be recorded during a period equal to one second in time. Many different ideas for improving the write performance have been suggested. One such method is a fast verify method, which reduces the operation time for verify among specific operations of the programming operation, which include a program pulse application operation and a verify operation.
The verify operation is an operation for determining whether a threshold voltage is shifted to a level desired for a cell after programming and the verify operation requires longer time than the program pulse application operation. Therefore, reducing the time required for the verify operation is an effective way to improve the write performance. A cycle of the verify operation includes a bit line precharge operation, an evaluation operation, and a sensing operation. The fast verify method requires a one-time bit line precharge operation and a plurality of evaluation operations and sensing operations. In short, the time required for verify is shortened by performing the verify operation multiple times while performing the bit line precharge operation just one time.
FIG. 1 illustrates a structure of a conventional cell array of a non-volatile memory device. Referring to FIG. 1, the non-volatile memory device includes a plurality of memory cells for storing data, a plurality of word lines WL, a plurality of bit lines BL, a page buffer 110, and a connector 120 for electrically coupling the bit lines BL with the page buffer 110. Herein, the memory cells are serially connected between a source selection transistor, which is a transistor receiving source selection line (SSL), and a drain selection transistor, which is transistor receiving drain selection line (DSL), to thereby form a string structure.
Hereafter, the verify operation, which is performed the same as the read operation, will be described. For the sake of convenience in description, it is assumed that a word line WL0 is selected and the verify operation is performed for a memory cell coupled with the word line WL0.
First, the page buffer 110 supplies a power source voltage VCC to a sensing node S0. Then, a precharge bias V1 is applied to a PBSENSE node of the connector 120. When the precharge bias V1 is applied, the connector 120 electrically connects the sensing node S0 with a bit line BL and accordingly the bit line BL is precharged to the level of the power source voltage VCC. This is referred to as “a bit line precharge operation.” During the precharge operation, the drain selection transistor is turned on while the source selection transistor is turned off.
Subsequently, a ground voltage VSS is applied to the PBSENSE node to electrically disconnect the page buffer 110 and a bit line BL from each other. A read voltage is applied to the word line WL0 and turn-on voltage is applied to the other word lines WL1 to WLN. Herein, the read voltage is a voltage for detecting a threshold voltage of a memory cell connected to the word line WL0, and the turn-on voltage is a voltage for turning on a transistor regardless of data recorded in a memory cell. Then, the potential of the bit line BL is maintained at the level of the power source voltage VCC or the potential of the bit line BL is not maintained at the level of the power source voltage VCC and dropped based on whether the memory cell coupled with the word line WL0 is properly programmed or not. This is called an evaluation operation. During the evaluation operation, both drain selection transistor and source selection transistor are all turned on.
After the evaluation operation, a sensing bias voltage V2 is applied to the PBSENSE node. As a result, the bit line BL and the page buffer 110 are electrically connected to each other, and the page buffer 110 senses the potential of the bit line BL and determines whether the memory cell is properly programmed or not. This is referred to as “a sensing operation.”
FIG. 2 is a timing diagram illustrating a conventional fast verify process. Referring to FIG. 2, WL represents the potential of a selected word line WL, and PBSENSE represents the gate potential of the connector 120. BL represents the potential of a bit line.
A reference numeral ‘210’ represents a precharge duration, during which the precharge voltage V1 is applied to the PBSENSE node to precharge the bit line BL to the level of the power source voltage VCC.
A reference numeral ‘220’ represents a first verify duration, which includes an evaluation section 221 and a sensing section 222. In examining the evaluation operation 221, a first read voltage VREAD1 is applied to the word line WL and the bit line BL is evaluated based on the first read voltage VREAD1. When the memory cell coupled with the word line WL is turned off, the potential of the bit line BL follows along the solid line in the drawing. When the memory cell coupled with the word line WL is turned on, the potential of the bit line BL follows along the dotted line in the drawing. This is the same in the second and third verify durations as well. In examining the operation in the sensing section 222, a sensing bias voltage V2 is applied to the PBSENSE node, and as a result, the bit line BL and the page buffer 110 are electrically connected to each other. Then, the page buffer 110 determines whether the potential of the bit line BL maintains the level of the initial precharge voltage VCC and performs a sensing operation.
Reference numerals ‘230’ and ‘240’ indicate the second and third verify operations, respectively. In the verify operations, a second read voltage VREAD2 and a third read voltage VREAD3 are applied, respectively, and the verify operations are performed through an evaluation section 231 or 241 and a sensing section 232 or 242.
A fast verify operation features a plurality of verify operations 220, 230 and 240 performed with one-time bit line precharge 210. However, a bit line BL inevitably has leakage current incurred therein and thus the precharge voltage VCC level cannot be maintained in the bit line BL. As to the solid line representing the potential of the bit line BL in the drawings, although the memory cell coupled with the word line WL is not turned on, the potential of the bit line BL does not maintain the initial precharge voltage VCC level and gradually drops. Since the potential of the bit line BL does not maintain the initial precharge voltage VCC level, there is a limitation in the number of verify operations performed during the fast verify operation. Particularly, since the amount of the leakage current increases at a high temperature, this raises a concern.